Increasing complexity of integrated circuits and increasing use of surface mount interconnection technology have led manufacturers of such integrated circuits to design them for easier testing using techniques such as the so-called "boundary scan" technique. It has been proposed to provide for standardized access to such integrated circuits for test purposes. The resulting standard, IEEE standard 1149.1, defines a standard serial bus access method employing the "boundary scan" technique which provides total control over an integrated circuit's input and output pins. This standard serial bus interface permits control of all of the integrated circuit's input/output operations, independently of the integrated circuit's function, and while the system is in its operating mode.
Boundary scan arrangements have been disclosed in the following papers: Colin Maundar and Frans Beenker, "BOUNDARY-SCAN: A Framework For Structured Design-For-Test," IEEE International Test Conference February 1987; Patrick P. Fasang, "Boundary Scan And Its Application To Analog-Digital ASIC Testing in a Board/System Environment," IEEE Custom Integrated Circuits Conference 1989.
Boundary scan integrated circuits compatible with IEEE 1149.1 comprise a scan cell in the signal path between each bonding pad or terminal and the core circuitry of the integrated circuit. In this specification, the term "core circuitry" refers to circuitry which is internal to the integrated circuit and which is to be tested. The scan cells are connected in series, i.e. in a chain, to a four wire interface known as the TAP interface, which permits access to the scan chain for testing purposes. The TAP interface comprises a series of shift registers, one to store instructions and the others to store test data to be used in accordance with those instructions. The scan chain comprises an external shift register connected between TAP interface ports.
Each scan cell comprises a storage device and a switch. In normal operation the switch connects the core circuitry to the pad or terminal to allow passage of normal functional signals. For test purposes, the switch connects the terminal pad or the core circuitry to the storage device. A reference binary vector stored in the chain of storage devices can thus be applied to the core circuitry or to the terminal pads of the integrated circuit.
This IEEE standard boundary scan design facilitates the testing of hardware, but is not entirely satisfactory for use when testing software, particularly diagnostic and maintenance software for monitoring the system's performance. Large and complex systems, such as telephone switches and data transmission equipment, have substantial portions of their operating software dedicated to maintenance and diagnostic functions. Typically, such systems are able to diagnose problems and, in some cases, initiate remedial action.
The maintenance and diagnostic software packages themselves are large, complex and vital systems. It is necessary to be able to test and verify the operation of these software packages. One way of doing so is to introduce faults deliberately into the hardware, see if they are detected and, where applicable, ensure that appropriate corrective action is taken. This procedure is known as "Fault Insertion". Clearly fault insertion must be done with the system in its normal operating configuration. Examples of fault insertion systems are disclosed in U.S. Pat. No. 4,669,081 dated May 26, 1987, inventors James K. Mathewes, Jr. et al and U.S. Pat. No. 4,875,209 dated Oct. 17, 1989, inventors James K. Mathewes, Jr. et al. Such fault insertion techniques generally are difficult to perform with adequate thoroughness in view of the size of the hardware systems involved (many thousands of nodes to which faults are to be applied) and the density of the packaging.
It is desirable to be able to use fault insertion testing in systems which employ IEEE standard 1149.1. Unfortunately, this is not possible because the IEEE standard 1149.1 boundary scan system does not easily permit individual input or output terminals of the integrated circuit to be accessed independently. Consequently, if a fault were to be inserted, all terminals would be affected and the integrated circuit would simply not function at all.